1. Field of the Invention
The invention relates to a high voltage semiconductor device, and in particular to a laterally diffused metal oxide semiconductor (LDMOS) transistor and a method for fabricating the same.
2. Description of the Related Art
High voltage semiconductor technology is applied to integrated circuits with high voltages and high power. Traditional high voltage semiconductor devices, such as vertically diffused metal oxide semiconductor (VDMOS) transistors and LDMOS transistors are mainly used for devices with at least 18 volts or higher. The advantages of high voltage device technology include cost effectiveness and process compatibility, and thus high voltage device technology has been widely used in display driver IC devices, and power supply devices, and the power management, communications, autotronics, and industrial control fields, etc.
LDMOS transistors typically control current flowing between a drain and a source by a channel resulting from the gate voltage. In a traditional LDMOS transistor, the channel length must be extended in order to prevent source-drain punch-through effect. However, device size increases with increased channel length, thereby resulting in increased chip area and increased on resistance (Ron). Moreover, since the mobility of a hole carrier is lower than that of the electron carrier, the on resistance of a p-type diffused metal oxide semiconductor (PDMOS) transistor is higher than that of an n-type diffused metal oxide semiconductor (NDMOS) transistor, and this is detrimental for performance enhancement of PDMOS transistors.
Accordingly, there exists a need in the art for development of an improved high voltage semiconductor device structure, capable of mitigating or addressing the above-described problems.